View 28F016S5_1570099.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

e product preview june 1997 order number: 290597-003 n smartvoltage technology ? smart 5 flash: 5v v cc and 5v or 12v v pp n high-performance ? 4, 8 mbit: 85 ns read access time ? 16 mbit: 95 ns read access time n enhanced data protection features ? absolute protection with v pp = gnd ? flexible block locking ? block write lockout during power transitions n enhanced automated suspend options ? program suspend to read ? block erase suspend to program ? block erase suspend to read n industry-standard packaging ? 40-lead tsop, 44-lead psop n high-density 64-kbyte symmetrical erase block architecture ? 4 mbit: eight blocks ? 8 mbit: sixteen blocks ? 16 mbit: thirty-two blocks n extended cycling capability ? 100,000 block erase cycles n low power management ? deep power-down mode ? automatic power savings mode decreases i cc in static mode n automated program and block erase ? command user interface ? status register n sram-compatible write interface n etox? v nonvolatile flash technology intels byte-wide smart 5 flashfile? memory family renders a variety of density offerings in the same package. the 4-, 8-, and 16-mbit byte-wide flashfile memories provide high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. their symmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, simms, and memory cards. enhanced suspend capabilities provide an ideal solution for code or data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the 4-, 8-, and 16-mbit flashfile memories offer three levels of protection: absolute protection with v pp at gnd, selective hardware block locking, or flexible software block locking. these alternatives give designers ultimate control of their code security needs. this family of products is manufactured on intels 0.4 m m etox? v process technology. they come in industry-standard packages: the 40-lead tsop, ideal for board-constrained applications, and the rugged 44-lead psop. based on the 28f008sa architecture, the byte-wide smart 5 flashfile memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. byte-wide smart 5 flashfile? memory family 4, 8, and 16 mbit 28f004s5, 28f008s5, 28F016S5 includes commercial and extended temperature specifications
information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 28f004s5, 28f008s5, 28F016S5 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from: intel corporation p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 or visit intels website at http:\\www.intel.com copyright ? intel corporation, 1997 cg-041493 * third-part y brands and names are the propert y of their respective owners
e byte-wide smart 5 flashfile? memory family 3 product preview contents page page 1.0 introduction .............................................5 1.1 new features...............................................5 1.2 product overview.........................................5 1.3 pinout and pin description ...........................6 2.0 principles of operation .......................9 2.1 data protection ..........................................10 3.0 bus operation .........................................10 3.1 read ..........................................................10 3.2 output disable ...........................................10 3.3 standby......................................................10 3.4 deep power-down .....................................10 3.5 read identifier codes operation ................11 3.6 write ..........................................................11 4.0 command definitions ............................11 4.1 read array command................................14 4.2 read identifier codes command ...............14 4.3 read status register command................14 4.4 clear status register command................14 4.5 block erase command ..............................14 4.6 program command....................................15 4.7 block erase suspend command................15 4.8 program suspend command .....................16 4.9 set block and master lock-bit commands 16 4.10 clear block lock-bits command..............17 5.0 design considerations ........................25 5.1 three-line output control..........................25 5.2 ry/by# hardware detection ......................25 5.3 power supply decoupling ..........................25 5.4 v pp trace on printed circuit boards...........25 5.5 v cc , v pp , rp# transitions .........................25 5.6 power-up/down protection ........................25 6.0 electrical specifications..................26 6.1 absolute maximum ratings........................26 6.2 commercial temperature operating conditions .................................................26 6.2.1 capacitance.........................................26 6.2.2 ac input/output test conditions .........27 6.2.3 commercial temperature dc characteristics..............................28 6.2.4 commercial temperature ac characteristics - read-only operations..........................................30 6.2.5 commercial temperature reset operations..........................................31 6.2.6 commercial temperature ac characteristics - write operations 32 6.2.7 commercial temperature block erase, program, and lock-bit configuration performance.......................................34 6.3 extended temperature operating conditions .................................................35 6.3.1 extended temperature dc characteristics..............................35 6.3.2 extended temperature ac characteristics - read-only operations..........................................35 appendix a. ordering information ..........36 appendix b. additional information........37
byte-wide smart 5 flashfile? memory family e 4 product preview revision history number description -001 original version -002 table 3 revised to reflect change in abbreviations from w for write to p for program. ordering information graphic (appendix a) corrected: from pb = ext. temp. 44-lead psop to tb = ext. temp. 44-lead psop updated ordering information and table correction to table, section 6.2.3. under i lo test conditions, previously read v in = v cc or gnd, corrected to v out = v cc or gnd section 6.2.7, modified program and block erase suspend latency times -003 updated disclaimer
e byte-wide smart 5 flashfile? memory family 5 product preview 1.0 introduction this datasheet contains 4-, 8-, and 16-mbit smart 5 flashfile memory specifications. section 1 provides a flash memory overview. sections 2, 3, 4, and 5 describe the memory organization and functionality. section 6 covers electrical specifications for commercial and extended temperature product offerings. the byte-wide smart 5 flashfile memory family documentation also includes application notes and design tools which are referenced in appendix b. 1.1 new features the byte-wide smart 5 flashfile memory family maintains backwards-compatibility with intels 28f008sa. key enhancements include: smartvoltage technology enhanced suspend capabilities in-system block locking they share a compatible status register, software commands, and pinouts. these similarities enable a clean upgrade from the 28f008sa to byte-wide smart 5 flashfile products. when upgrading, it is important to note the following differences: because of new feature and density options, the devices have different device identifier codes. this allows for software optimization. v pplk has been lowered from 6.5v to 1.5v to support low v pp voltages during block erase, program, and lock-bit configuration operations. designs that switch v pp off during read operations should transition v pp to gnd. to take advantage of smartvoltage tech- nology, allow v pp connection to 5v. for more details see application note ap-625, 28f008sc compatibility with 28f008sa (order number 292180) . 1.2 product overview the byte-wide smart 5 flashfile memory family provides density upgrades with pinout compatibility for the 4-, 8-, and 16-mbit densities. the 28f004s5, 28f008s5, and 28F016S5 are high-performance memories arranged as 512 kbyte, 1 mbyte, and 2 mbyte of 8 bits. this data is grouped in eight, sixteen, and thirty-two 64-kbyte blo cks which are individually erasable, lockable, and unlockable in- system. figure 4 illustrates the memory organization. smartvoltage technology enables fast factory programming and low power designs. specifically designed for 5v systems, smart 5 flashfile components support read operations at 5v v cc and block erase and program operations at 5v and 12v v pp . the 12v v pp option renders the fastest program performance which will increase your factory throughput. with the 5v v pp option, v cc and v pp can be tied together for a simple 5v design. in addition to the voltage flexibility, the dedicated v pp pin gives complete data protection when v pp v pplk . internal v pp detection circuitry automatically configures the device for optimized block erase and program operations. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. a block erase operation erases one of the devices 64-kbyte blocks typically within 1 second (12v v pp ), independent of other blo cks. each block can be independently erased 100,000 times (1.6 million block erases per device). a block erase suspend operation allows system software to suspend block erase to read data from or program data to any other block. data is programmed in byte increments typically within 6 m s (12v v pp ). a program suspend operation permits system software to r ead data or execute code from any other flash memory array location.
byte-wide smart 5 flashfile? memory family 6 product preview to protect programmed data, each block can be locked. this block locking mechanism uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock individual blocks. the block lock-bits gate block erase and program operations, while the master lock-bit gates block lock-bit configuration operations. lock-bit config- uration operations (set block lock-bit, set master lock-bit, and clear block lock-bits commands) set and clear lock-bits. the status register and ry/by# output indicate whether or not the device is busy executing or ready for a new command. polling the status register, system software retrieves wsm feedback. the ry/by# output gives an additional indicator of wsm activity by providing a hardware status signal. like the status register, ry/by#-low indicates that the wsm is performing a block erase, program, or lock-bit configuration. ry/by#-high indicates that the wsm is ready for a new command, block erase is suspended (and program is inactive), program is suspended, or the device is in deep power-down mode. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 1 ma. when ce# and rp# pins are at v cc , the component enters a cmos standby mode. driving rp# to gnd enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. 1.3 pinout and pin description the family of devices is available in 40-lead tsop (thin small outline package, 1.2 mm thick) and 44-lead psop (plastic small outline package). pinouts are shown in figures 2 and 3. 4 - m b i t : a - a , 8 - m b i t : a - a , 1 6 - m b i t : a - a 0 1 8 0 1 9 0 2 0 i n p u t b u f f e r o u t p u t b u f f e r i d e n t i f i e r r e g i s t e r s t a t u s r e g i s t e r c o m m a n d r e g i s t e r i / o l o g i c d a t a c o m p a r a t o r i n p u t b u f f e r a d d r e s s l a t c h a d d r e s s c o u n t e r y d e c o d e r x d e c o d e r y g a t i n g 4 - m b i t : e i g h t 8 - m b i t : s i x t e e n 1 6 - m b i t : t h i r t y - t w o 6 4 - k b y t e b l o c k s w r i t e s t a t e m a c h i n e p r o g r a m / e r a s e v o l t a g e s w i t c h c e # w e # o e # r p # r y / b y # v v g n d d q - d q p p c c v c c 0 7 figure 1 . block diagram
e byte-wide smart 5 flashfile? memory family 7 product preview table 1. pin descriptions sym type name and function a 0 Ca 20 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. 4 mbit ? a 0 ?a 18 8 mbit ? a 0 ?a 19 16 mbit ? a 0 Ca 20 dq 0 Cdq 7 input/ output data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register, and identifier code read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. ce# input chip enable: activates the devices control logic, input buffers, decoders, and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. rp# input reset/deep power-down: when driven low, rp# inhibits write operations which provides data protection during power transitions, puts the device in deep power-down mode, and resets internal automation. rp#-high enables normal operation. exit from deep power-down sets the device to read array mode. rp# at v hh enables setting of the master lock-bit and enables configuration of block lock-bits when the master lock-bit is set. rp# = v hh overrides block lock-bits, thereby enabling block erase and program operations to locked memory blocks. block erase, program, or lock-bit configuration with v ih < rp# < v hh produce spurious results and should not be attempted. oe# input output enable: gates the devices outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. ry/by# output ready/busy#: indicates the status of the internal wsm. when low, the wsm is performing an internal operation (block erase, program, or lock-bit configuration). ry/by#-high indicates that the wsm is ready for new commands, block erase or program is suspended, or the device is in deep power-down mode. ry/by# is always active. v pp supply block erase, program, lock-bit configuration power supply: for erasing array blocks, programming data, or configuring lock-bits. smart 5 flash ? 5v and 12v v pp with v pp v ppl k , memory contents cannot be altered. block erase, program, and lock-bit configuration with an invalid v pp (see dc characteristics) produce spurious results and should not be attempted. v cc supply device power supply: internal detection automatically configures the device for optimized read performance. do not float any power pins. smart 5 flash ? 5v v cc with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltages (see dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated.
byte-wide smart 5 flashfile? memory family e 8 product preview 28f004s5 28f008s5 28F016S5 nc ce# rp# a 18 a 13 a 17 a 14 a 16 a 15 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 v cc v pp nc we# oe# ry/by# gnd gnd dq 6 dq 7 dq 5 a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 nc v cc a 19 a 19 dq 4 a 20 40-lead tsop standard pinout 10 mm x 20 mm top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 40 39 38 37 36 35 34 33 ce# rp# a 18 a 13 a 17 a 14 a 16 a 15 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 v cc v pp ce# rp# a 18 a 13 a 17 a 14 a 16 a 15 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 v cc v pp nc we# oe# ry/by# gnd gnd dq 6 dq 7 dq 5 a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 nc v cc dq 4 nc we# oe# ry/by# gnd gnd dq 6 dq 7 dq 5 a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 v cc dq 4 figure 2. tsop 40-lead pinout a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 nc nc gnd gnd v pp 28f004s5 28f008s5 28F016S5 a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 nc nc gnd gnd v pp we# ce# ry/by# dq 6 dq 7 dq 5 nc v cc a 18 a 13 a 17 a 14 a 16 a 15 a 12 nc nc nc nc oe# v cc dq 4 a 19 a 19 a 20 44-lead psop 13.3 mm x 28.2 mm top view 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 41 42 43 44 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a 0 a 1 a 2 a 3 dq 3 dq 2 dq 1 dq 0 rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 nc nc gnd gnd v pp we# ce# ry/by# dq 6 dq 7 dq 5 v cc a 18 a 13 a 17 a 14 a 16 a 15 a 12 nc nc nc oe# v cc dq 4 we# ce# ry/by# dq 6 dq 7 dq 5 v cc a 18 a 13 a 17 a 14 a 16 a 15 a 12 nc nc nc nc oe# v cc dq 4 figure 3. psop 44-lead pinout
e byte-wide smart 5 flashfile? memory family 9 product preview 2.0 principles of operation the byte-wide smart 5 flashfile memories include an on-chip wsm to manage block erase, program, and lock-bit configuration functions. it allows for: 100% ttl-level control inputs, fixed power supplies during block erasure, program, and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from deep power-down mode (see bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby, and output disable operations. status register and identifier codes can be accessed through the cui independent of the v pp voltage. high voltage on v pp enables successful block erasure, program, and lock-bit configuration. all functions associated with altering memory contents block erase, program, lock-bit configuration, status, and identifier codesare accessed via the cui and verified through the status register. commands are written using standard micro- processor write timings. the cui contents serve as input to the wsm that controls block erase, program, and lock-bit configuration operations. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read data from or program data to any other block. program suspend allows system software to sus pend a program to read data from any other flash memory array location. 64-kbyte block 1fffff 31 1f0000 1effff 1e0000 1dffff 1d0000 1cffff 1c0000 1bffff 30 29 28 27 1b0000 1affff 1a0000 19ffff 190000 18ffff 180000 17ffff 26 25 24 23 170000 16ffff 160000 15ffff 150000 14ffff 140000 13ffff 22 21 20 19 130000 12ffff 120000 11ffff 110000 10ffff 100000 0fffff 18 17 16 15 0f0000 0effff 0e0000 0dffff 0d0000 0cffff 0c0000 0bffff 14 13 12 11 0b0000 0affff 0a0000 09ffff 090000 08ffff 080000 07ffff 10 9 8 7 070000 06ffff 060000 05ffff 050000 04ffff 040000 03ffff 6 5 4 3 030000 02ffff 020000 01ffff 010000 00ffff 000000 2 1 0 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 64-kbyte block 8-mbit 16-mbit 4-mbit figure 4. memory map
byte-wide smart 5 flashfile? memory family e 10 product preview 2.1 data protection depending on the application, the system desi gner may choose to make the v pp power supply switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to v pph1/2 . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pp v pplk , memory contents cannot be altered. when high voltage is applied to v pp , the two-step block erase, program, or lock-bit configuration command sequences provides pro- tection from unwanted operations. all write functions are disabled when v cc voltage is below the write lockout voltage v lko or when rp# is at v il . the devices block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations. 3.0 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read block information, identifier codes, or status register can be read independent of the v pp voltage. rp# can be at either v ih or v hh . the first task is to write the appropriate read-mode command (read array, read identifier codes, or read status register) to the cui. upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read array mode. four control pins dictate the data flow in and out of the component: ce#, oe#, we#, and rp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 Cdq 7 ) control and when active drives the selected memory data onto the i/o bus. we# must be at v ih and rp# must be at v ih or v hh . figure 15 illustrates a read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0 Cdq 7 are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 Cdq 7 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, program, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes. 3.4 deep power-down rp# at v il initiates the deep power-down mode. in read mode, rp#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. rp# must be held low for time t plph . time t phqv is required after return from power-down until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui resets to read array mode, and the status register is set to 80h. during block erase, program, or lock-bit configuration, rp#-low will abort the operation. ry/by# remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. intels flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
e byte-wide smart 5 flashfile? memory family 11 product preview 000000 block 0 master lock configuration 000001 000002 000003 010000 010002 00ffff device code block 0 lock configuration manufacturer code reserved for future implementation block 1 block 1 lock configuration reserved for future implementation 01ffff reserved for future implementation 1f0000 1f0002 block 31 lock configuration reserved for future implementation 1fffff block 31 (blocks 16 through 30) (blocks 8 through 14) (blocks 2 through 14) 070000 070002 block 7 block 7 lock configuration reserved for future implementation 07ffff reserved for future implementation 0f0000 0f0002 block 15 block 15 lock configuration reserved for future implementation 0fffff 8-mbit 16-mbit 4-mbit reserved for future implementation reserved for future implementation figure 5. device identifier code memory map 3.5 read identifier codes operation the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and master lock configuration code (see figure 5). using the manufacturer and device codes, the system software can automatically match the device with its proper algorithms. the block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 3.6 write the cui does not occupy an addressable memory location. it is written when we# and ce# are active and oe# = v ih . the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figure 17 illustrates a write operation. 4.0 command definitions when the v pp voltage v pplk , read operations from the status register, identifier codes, or blocks are enabled. placing v pph1/2 on v pp enables successful block erase, program, and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 3 defines these commands.
byte-wide smart 5 flashfile? memory family e 12 product preview table 2. bus operations mode notes rp# ce# oe# we# address v pp dq 0 C7 ry/by# read 1,2,3 v ih or v hh v il v il v ih xxd out x output disable 3 v ih or v hh v il v ih v ih x x high z x standby 3 v ih or v hh v ih x x x x high z x deep power-down 4 v il x x x x x high z v oh read identifier codes v ih or v hh v il v il v ih see figure 5 x note 5 v oh write 3,6,7 v ih or v hh v il v ih v il xxd in x notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address input pins and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. ry/by# is v ol when the wsm is executing internal block erase, program, or lock-bit configuration algorithms. it is v oh when the wsm is not busy, in block erase suspend mode (with program inactive), program suspend mode, or deep power- down mode. 4. rp# at gnd 0.2v ensures the lowest deep power-down current. 5. see section 4.2 for read identifier code data. 6. command writes involving block erase, program, or lock-bit configuration are reliably executed when v pp = v pph1/2 and v cc = v cc1/2 (see section 6.2 for operating conditions). 7. refer to table 3 for valid d in during a write operation.
e byte-wide smart 5 flashfile? memory family 13 product preview table 3. command definitions (9) bus cycles first bus cycle second bus cycle command req'd. notes oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array/reset 1 write x ffh read identifier codes 3 2 4 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write ba 20h write ba d0h program 2 5,6 write pa 40h or 10h write pa pd block erase and program suspend 1 5 write x b0h block erase and program resume 1 5 write x d0h set block lock-bit 2 7 write ba 60h write ba 01h set master lock-bit 2 7 write x 60h write x f1h clear block lock-bits 2 8 write x 60h write x d0h notes: 1. bus operations are defined in table 2. 2. x = any valid address within the device. ia = identifier code address: see figure 5. ba = address within the block being erased or locked. pa = address of memory location to be programmed. 3. srd = data read from status register. see table 6 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we# or ce# (whichever goes high first). id = data read from identifier codes. 4. following the read identifier codes command, read operations access manufacturer, device, block lock, and master lock codes. see section 4.2 for read identifier code data. 5. if the block is locked, rp# must be at v hh to enable block erase or program operations. attempts to issue a block erase or program to a locked block while rp# is v ih will fail. 6. either 40h or 10h are recognized by the wsm as the program setup. 7. if the master lock-bit is set, rp# must be at v hh to set a block lock-bit. rp# must be at v hh to set the master lock-bit. if the master lock-bit is not set, a block lock-bit can be set while rp# is v ih . 8. if the master lock-bit is set, rp# must be at v hh to clear block lock-bits. the clear block lock-bits operation simultaneously clears all block lock-bits. if the master lock-bit is not set, the clear block lock-bits command can be done while rp# is v ih . 9. commands other than those shown above are reserved by intel for future device implementations and should not be used.
byte-wide smart 5 flashfile? memory family e 14 product preview 4.1 read array command upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, program or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or program suspend command. the read array command functions independently of the v pp voltage and rp# can be v ih or v hh . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 5 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see table 4 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pp voltage and rp# can be v ih or v hh . following the read identifier codes command, the subsequent information can be read. table 4. identifier codes code address data manufacturer code 000000 89 4-mbit 000001 a7 device code 8-mbit 000001 a6 16-mbit 000001 aa block lock configuration xx 0002 (1) block is unlocked dq 0 = 0 block is locked dq 0 = 1 reserved for future use dq 1 C7 master lock configuration 000003 device is unlocked dq 0 = 0 device is locked dq 0 = 1 reserved for future use dq 1C7 note: 1. x selects the specific block lock configuration code to be read. see figure 5 for the device identifier code memory map. 4.3 read status register command the status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs first. oe# or ce# must toggle to v ih to update the status register latch. the read status register command functions independently of the v pp voltage. rp# can be v ih or v hh . 4.4 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 6). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pp voltage. rp# can be v ih or v hh . this command is not functional during block erase or program suspend modes. 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle comm and. a block erase setup is written first, followed by a block erase confirm. this command sequence requires appropriate se- quencing and an address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase s equence is written, the device automatically outputs status register data when read (see figure 6). the cpu can detect block erase completion by analyzing the ry/by# pin or status register bit sr.7.
e byte-wide smart 5 flashfile? memory family 15 product preview when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. also, reliable block erasure can only occur when v cc = v cc1/2 and v pp = v pph1/2 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr.3 and sr.5 will be set to 1. successful block erase requires that the corresponding block lock-bit be cleared or, if set, that rp# = v hh . if block erase is attempted when the corresponding block lock-bit is set and rp# = v ih , the block erase will fail, and sr.1 and sr.5 will be set to 1. block erase operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.6 program command program is executed by a two-cycle command sequence. program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the program and write verify algorithms internally. after the program sequence is written, the device automatically outputs status register data when read (see figure 7). the cpu can detect the completion of the program event by analyzing the ry/by# pin or status register bit sr.7. when program is complete, status register bit sr.4 should be checked. if program error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until it receives another command. reliable programs only occurs when v cc = v cc1/2 and v pp = v pph1/2 . in the absence of this high voltage, memory contents are protected against programs. if program is attempted while v pp v pplk , the operation will fail, and status register bits sr.3 and sr.5 will be set to 1. successful program also requires that the corresponding block lock-bit be cleared or, if set, that rp# = v hh . if program is attempted when the corresponding block lock-bit is set and rp# = v ih , program will fail, and sr.1 and sr.4 will be set to 1. program operations with v ih < rp# < v hh produce spurious results and should not be attempted. 4.7 block erase suspend command the block erase suspend command allows block-erase interruption to read data from or program data to another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to 1). ry/by# will also transition to v oh . specification t whrh2 defines the block erase suspend latency. at this point, a read array command can be written to read data from blo cks other t han that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. using the program sus pend command (see section 4.8), a program operation can also be suspended. during a program operation with block erase suspended, status register bit sr.7 will return to 0 and the ry/by# output will transition to v ol . however, sr.6 will remain 1 to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/by# will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see figure 8). v pp must remain at v pph1/2 (the same v pp level used for block erase) while block erase is suspended. rp# must also remain at v ih or v hh (the same rp# level used for block erase). block erase cannot resume until program operations initiated during block erase suspend have completed.
byte-wide smart 5 flashfile? memory family e 16 product preview 4.8 program suspend command the program suspend command allows program interruption to read data in other flash memory locations. once the program process starts, writing the program suspend command requests that the wsm suspend the program sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the program suspend command is written. polling status register bits sr.7 and sr.2 can determine when the program operation has been suspended (both will be set to 1). ry/by# will also transition to v oh . specification t whrh1 defines the program suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while program is suspended are read status register and program resume. after program resume command is written to the flash memory, the wsm will continue the program process. status register bits sr.2 and sr.7 will automatically clear and ry/by# will return to v ol . after the program resume command is written, the device automatically outputs status register data when read (see figure 9). v pp must remain at v pph1/2 (the same v pp level used for program) while in program suspend mode. rp# must also remain at v ih or v hh (the same rp# level used for program). 4.9 set block and master lock-bit commands a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. the block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. with the master lock-bit not set, individual block lock-bits can be set using the set block lock-bit command. the set master lock-bit command, in conjunction with rp# = v hh , sets the master lock-bit. after the master lock-bit is set, subsequent setting of block lock-bits requires both the set block lock-bit command and v hh on the rp# pin. see table 5 for a summary of hardware and software write protection options. set block lock-bit and master lock-bit are initiated using two-cycle comm and sequence. the set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 10). the cpu can detect the completion of the set lock-bit event by analyzing the ry/by# pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. an invalid set block or master lock-bit command will result in status register bits sr.4 and sr.5 being set to 1. also, reliable operations occur only when v cc = v cc1/2 and v pp = v pph1/2 . in the absence of this high voltage, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that rp# = v hh . if it is attempted with the master lock-bit set and rp# = v ih , the operation will fail, and sr.1 and sr.4 will be set to 1. a successful set master lock-bit operation requires that rp# = v hh . if it is attempted with rp# = v ih , the operation will fail, and sr.1 and sr.4 will be set to 1. set block and master lock-bit operations with v ih < rp# < v hh produce spurious results and should not be attempted.
e byte-wide smart 5 flashfile? memory family 17 product preview 4.10 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. with the master lock-bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the master lock-bit is set, clearing block lock-bits requires both the clear block lock-bits command and v hh on the rp# pin. see table 5 for a summary of hardware and software write protection options. clear block lock-bits operation is initiated using a two-cycle comm and sequence. a clear block lock-bits setup is written first. then, the device automatically outputs status register data when read (see figure 11). the cpu can detect completion of the clear block lock-bits event by analyzing the ry/by# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. also, a reliable clear block lock-bits operation can only occur when v cc = v cc1/2 and v pp = v pph1/2 . if a clear block lock-bits operation is attempted while v pp v pplk , sr.3 and sr.5 will be set to 1. in the absence of this high voltage, the block lock-bits content are protected against alteration. a suc- cessful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock- bit is set, that rp# = v hh . if it is attempted with the master lock-bit set and rp# = v ih , sr.1 and sr.5 will be set to 1 and the operation will fail. a clear block lock-bits operation with v ih < rp# < v hh produce spurious results and should not be attempted. if a clear block lock-bits operation is aborted due to v pp or v cc transitioning out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock- bits is required to initialize block lock-bit contents to known values. once the master lock-bit is set, it cannot be cleared. table 5. write protection alternatives operation master lock-bit bloc k lock-bit rp# effect block erase or 0 v ih or v hh block erase and program enabled program x 1 v ih block is locked. block erase and program disabled v hh block lock-bit override. block erase and program enabled set block 0 x v ih or v hh set block lock-bit enabled lock-bit 1 x v ih master lock-bit is set. set block lock-bit disabled v hh master lock-bit override. set block lock-bit enabled set master x x v ih set master lock-bit disabled lock-bit v hh set master lock-bit enabled clear block 0 x v ih or v hh clear block lock-bits enabled lock-bits 1 x v ih master lock-bit is set. clear block lock-bits disabled v hh master lock-bit override. clear block lock-bits enabled
byte-wide smart 5 flashfile? memory family e 18 product preview table 6. status register definition wsms ess eclbs pslbs vpps pss dps r 76543210 notes: sr.7 = write state machine status 1 = ready 0 = busy check ry/by# or sr.7 to determine block erase, program, or lock-bit configuration completion. sr.6 C0 are invalid while sr.7 = 0. sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.4 = program and set lock-bit status 1 = error in program or set master/block lock-bit 0 = successful program or set master/block lock-bit sr.3 = v pp status 1 = v pp low detect, operation abort 0 = v pp ok sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after a block erase, program, or lock- bit configuration operation. sr.3 is not guaranteed to reports accurate feedback only when v pp 1 v pph1/2 . sr.2 = program suspend status 1 = program suspended 0 = program in progress/completed sr.1 = device protect status 1 = master lock-bit, block lock-bit and/or rp# lock detected, operation abort 0 = unlock sr.1 does not provide a continuous indication of master and block lock-bit values. the wsm interrogates the master lock-bit, block lock-bit, and rp# only after a block erase, program, or lock-bit configuration operation. it informs the system, depending on the attempted operation, if the block lock-bit is set, master lock-bit is set, and/or rp# 1 v hh . sr.0 = reserved for future enhancements sr.0 is reserved for future use and should be masked out when polling the status register.
e byte-wide smart 5 flashfile? memory family 19 product preview sr.7 = 0 1 start write 20h, block address write d0h, block address full status check if desired block erase complete full status check procedure 1 0 read status register data (see above) 1 0 read status register suspend block erase suspend block erase loop yes no 1 0 command sequence error sr.3 = sr.5 = sr.4,5 = block erase error bus operation command comments standby check sr.4,5 both 1 = command sequence error standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1 = block erase error standby bus operation command comments write write erase setup read data = 20h addr = within block to be erased check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent block erasures. full status check can be done after each block erase, or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. status register data standby erase confirm data = d0h addr = within block to be erased block erase successful standby check sr.1 1 = device protect detect rp# = v ih , block lock-bit is set only required for systems implementing lock-bit configuration 0 1 device protect error sr.1 = check sr.3 1 = v pp error detect v pp range error figure 6. automated block erase flowchart
byte-wide smart 5 flashfile? memory family e 20 product preview sr.7 = 0 1 start write 40h, address write byte data and address full status check if desired program complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v range error bus operation command comments standby standby check sr.3 1 = v error detect sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write setup program data = data to be programmed addr = location to be programmed read data = 40h addr = location to be programmed check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent byte writes. sr full status check can be done after each program, or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. standby sr.3 = sr.4 = program error program successful program status register data suspend program yes no suspend program loop standby check sr.4 1 = program error 0 1 device protect error sr.1 = pp check sr.1 1 = device protect detect rp# = v , block lock-bit is set only required for systems implementing lock-bit configuration ih pp figure 7. automated program flowchart
e byte-wide smart 5 flashfile? memory family 21 product preview sr.7 = 0 1 start write b0h read status register write d0h block erase resumed bus operation command comments write erase suspend read data = b0h addr = x check sr.7 1 = wsm ready 0 = wsm busy status register data addr = x standby sr.6 = block erase completed write ffh read array data yes 0 1 check sr.6 1 = block erase suspended 0 = block erase completed standby data = d0h addr = x write erase resume read or program ? done? program loop read array data read program no figure 8. block erase suspend/resume flowchart
byte-wide smart 5 flashfile? memory family e 22 product preview sr.7 = 0 1 start write b0h read status register write d0h program resumed bus operation command comments write program suspend read data = b0h addr = x check sr.7 1 = wsm ready 0 = wsm busy status register data addr = x standby sr.2 = write ffh read array data done reading program completed write ffh read array data yes no 0 1 check sr.2 1 =program suspended 0 = program completed standby data = ffh addr = x write read array locations other than that being data written. read data = d0h addr = x write read array program resume figure 9. program suspend/resume flowchart
e byte-wide smart 5 flashfile? memory family 23 product preview sr.7 = 0 1 start write 60h, block/device address write 01h/f1h, block/device address full status check if desired set lock-bit complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error 1 0 command sequence error sr.3 = sr.4 = sr.4,5 = set lock-bit error bus operation command comments standby check sr.4,5 both 1 = command sequence error standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1 = set lock-bit reset error standby bus operation command comments write write set block/master lock-bit setup read data = 60h addr = block address (block), device address (master) check sr.7 1 = wsm ready 0 = wsm busy repeat for subsequent lock-bit set operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. write ffh after the last lock-bit set operation to place device in read array mode. status register data standby set block or master lock-bit confirm data = 01h (block), f1h (master) addr = block address (block), device address (master) set lock-bit successful standby 0 1 device protect error sr.1 = check sr.3 1 = v pp error detect check sr.1 1 = device protect detect rp# = v ih , (set master lock-bit operation) rp# = v hh , master lock-bit is set (set block lock-bit operation) figure 10. set block and master lock-bit flowchart
byte-wide smart 5 flashfile? memory family e 24 product preview sr.7 = 0 1 start write 60h write d0h full status check if desired clear block lock-bits complete full status check procedure 1 0 read status register data (see above) 1 0 read status register v pp range error bus operation command comments standby standby sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attempting retry or other error recovery. bus operation command comments write write clear block lock-bits setup data = d0h addr = x read data = 60h addr = x check sr.7 1 = wsm ready 0 = wsm busy write ffh after the clear block lock-bits operation to place device in read array mode. standby sr.3 = sr.5 = clear block lock-bits error clear block lock-bits successful clear block lock-bits confirm status register data standby check sr.5 1 = clear block lock bits error 0 1 device protect error sr.1 = 1 0 sr.4,5 = command sequence error check sr.4,5 both 1 = command sequence error standby check sr.1 1 = device protect detect rp# = v ih , master lock-bit is set check sr.3 1 = v pp error detect figure 11. clear block lock-bits flowchart
e byte-wide smart 5 flashfile? memory family 25 product preview 5.0 design considerations 5.1 three-line output control intel provides three control inputs to accommodate multiple memory connections: ce#, oe#, and rp#. three-line control provides for: a. lowest possible memory power dissipation. b. data bus contention avoidance. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs while de- selected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by# hardware detection ry/by# is a full cmos output that provides a hardware method of detecting block erase, program and lock-bit configuration completion. this output can be directly connected to an interrupt input of the system cpu. ry/by# transitions low w hen the wsm is busy and returns to v oh when it is finished executing the internal algorithm. during suspend and deep power-down modes, ry/by# remains at v oh . 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues: standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. these high-frequency, low-inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the arrays power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v pp trace on printed circuit boards updating flash memories that reside in the target system r equires that the printed circuit board designer pay attention to the v pp power supply trace. the v pp pin supplies the memory cell current for byte writing and block erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v pp supply traces and decoupling will decrease v pp voltage spikes and overshoots. 5.5 v cc , v pp , rp# transitions block erase, program and lock-bit configuration are not guaranteed if v pp or v cc fall outside of a valid voltage range (v cc1/2 and v pph1/2 ) or rp# 1 v ih or v hh . if v pp error is detected, status register bit sr.3 is set to 1 along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase, program, or lock-bit configuration, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power- down. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. 5.6 power-up/down protection the device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. upon power- up, the device is indifferent as to which power supply (v pp or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system desi gner must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and ce# must be low for a command write, driving either input signal to v ih will inhibit writes. the cuis two-step command sequence architecture provides an added level of protection against data alteration. in-system block lock and unlock renders additional protection during power-up by prohibiting block erase and program operations. the device is disabled while rp# = v il regardless of its control inputs state.
byte-wide smart 5 flashfile? memory family e 26 product preview 6.0 electrical specifications 6.1 absolute maximum ratings* temperature under bias ................. C10c to +80c storage temperature....................C65c to +125c voltage on any pin (except v pp, and rp#)............C2.0v to +7.0v (2) v pp voltage ............................. C2.0v to +14.0v (1,2) rp# voltage .......................... C2.0v to +14.0v (1,2,4) output short circuit current .................... 100 ma (3) notice: this datasheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local intel sales office that you have the latest datasheet before finalizing a design. *warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability . notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is C0.5v on input/output pins and C0.2v on v cc , rp#, and v pp pins. during transitions, this level may undershoot to C2.0v for periods <20 ns. maximum dc voltage on input/output pins and v cc is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20 ns. 2. maximum dc voltage on v pp and rp# may overshoot to +14.0v for periods <20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. rp# voltage is normally at v il or v ih . connection to supply of v hh is allowed for a maximum cumulative period of 80 hours. 6.2 commercial temperature operating conditions commercial temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature 0 +70 c ambient temperature v cc1 v cc supply voltage (5v 5%) 4.75 5.25 v v cc2 v cc supply voltage (5v 10%) 4.50 5.50 v 6.2.1 capacitance (1) t a = +25c, f = 1 mhz symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0v c out output capacitance 8 12 pf v out = 0.0v note: 1. sampled, not 100% tested.
e byte-wide smart 5 flashfile? memory family 27 product preview 6.2.2 ac input/output test conditions test points input output 1.5 3.0 0.0 1.5 ac test inputs are driven at 3.0v for a logic "1" and 0.0v for a logic "0." input timing begins, and output timing ends, at 1.5 v. input rise and fall times (10% to 90%) <10 ns. figure 12. transient input/output reference waveform for v cc = 5.0v 5% (high speed testing configuration) test points input output 2.0 0.8 0.8 2.0 2.4 0.45 ac test inputs are driven at v oh (2.4 v ttl ) for a logic "1" and v ol (0.45 v ttl ) for a logic "0." input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. figure 13. transient input/output reference waveform for v cc = 5.0v 10% (standard testing configuration) device under test 1.3v 1n914 r l c l out = 3.3 k note: c l includes jig capacitance figure 14. transient equivalent testing load circuit test configuration capacitance loading value test configuration c l (pf) v cc = 5.0v 5% 30 v cc = 5.0v 10% 100
byte-wide smart 5 flashfile? memory family e 28 product preview 6.2.3 commercial temperature dc characteristics commercial temperature dc characteristics for 4-, 8-, and 16-mbit smart 5 flashfile? memories 5.0v v cc test sym parameter notes typ max unit conditions i li input load current 1 1 m av cc = v cc max, v in = v cc or gnd i lo output leakage current 1 10 m av cc = v cc max, v out = v cc or gnd i ccs v cc standby current 1,3,6 25 100 m a cmos inputs v cc = v cc max ce# = rp# = v cc 0.2v 0.4 2 ma ttl inputs v cc = v cc max, ce# = rp# = v ih i ccd v cc deep power-down current 110 m a rp# = gnd 0.2v i out (ry/by#) = 0 ma i ccr v cc read current 1,5,6 17 35 ma cmos inputs v cc = v cc max, ce# = gnd f = 8 mhz, i out = 0 ma 20 50 ma ttl inputs v cc = v cc max, ce# = gnd f = 8 mhz, i out = 0 ma i ccw v cc program/set 1,7 35 ma v pp = 5.0v 10% lock-bit current 30 ma v pp = 12.0v 5% i cce v cc block erase/clear 1,7 30 ma v pp = 5.0v 10% block lock-bits current 25 ma v pp = 12.0v 5% i ccws i cces v cc program/block erase suspend current 1,2 1 10 ma ce# = v ih i pps v pp standby current 1 2 15 a v pp v cc i ppr v pp read current 1 10 200 a v pp > v cc i ppd v pp deep power-down current 1 0.1 5 a rp# = gnd 0.2v i ppw v pp program or 1,7 40 ma v pp = 5.0v 10% set lock-bit current 15 ma v pp = 12.0v 5% i ppe v pp block erase or clear 1,7 20 ma v pp = 5.0v 10% block lock-bits current 15 ma v pp = 12.0v 5% i ppws i ppes v pp program or block erase suspend current 1 10 200 a v pp = v pph1/2
e byte-wide smart 5 flashfile? memory family 29 product preview commercial temperature dc characteristics for 4-, 8-, and 16-mbit smart 5 flashfile? memories (continued) 5.0v v cc test sym parameter notes min max unit conditions v il input low voltage 7 C0.5 0.8 v v ih input high voltage 7 2.0 v cc + 0.5 v v ol output low voltage 3,7 0.45 v v cc = v cc min i ol = 5.8 ma v oh1 output high voltage (ttl) 3,7 2.4 v v cc = v cc min i oh = C2.5 ma v oh2 output high voltage (cmos) 3,7 0.85 v cc vv cc = v cc min i oh = C2.5 ma v cc C0.4 vv cc = v cc min i oh = C100 a v pplk v pp lockout voltage 4,7 1.5 v v pph1 v pp voltage 4.5 5.5 v v pph2 v pp voltage 11.4 12.6 v v lko v cc lockout voltage 2.0 v v hh rp# unlock voltage 8,9 11.4 12.6 v set master lock-bit override lock-bit notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25 c. these currents are valid for all product versions (packages and speeds). 2. i ccws and i cces are specified with the device de-selected. if read or written while in erase suspend mode, the devices current is the sum of i ccws or i cces and i ccr or i ccw . 3. includes ry/by#. 4. block erases, programs, and lock-bit configurations are inhibited when v pp v pplk , and not guaranteed in the range between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min), and above v pph2 (max). 5. automatic power savings (aps) reduces typical i ccr to 1 ma in static operation. 6. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 7. sampled, not 100% tested. 8. master lock-bit set operations are inhibited when rp# = v ih . block lock-bit configuration operations are inhibited when the master lock-bit is set and rp# = v ih . block erases and programs are inhibited when the corresponding block-lock bit is set and rp# = v ih . block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with v ih < rp# < v hh . 9. rp# connection to a v hh supply is allowed for a maximum cumulative period of 80 hours.
byte-wide smart 5 flashfile? memory family e 30 product preview 6.2.4 commercial temperature ac characteristics - read-only operations (1) commercial temperature read-only operations for 4-, 8-, and 16-mbit smart 5 flashfile? memories at t a = 0c to +70c 5v 5% v cc C85/C95 (5) ?? versions (4) 5v 10% v cc ? C90/C100 (6) C120 (6) # sym parameter notes min max min max min max unit r1 t avav read cycle time 4, 8 mbit 85 90 120 ns 16 mbit 95 100 120 ns r2 t avqv address to output 4, 8 mbit 85 90 120 ns delay 16 mbit 95 100 120 ns r3 t elqv ce# to output delay 4, 8 mbit 2 85 90 120 ns 16 mbit 2 95 100 120 ns r4 t glqv oe# to output delay 2 40 45 50 ns r5 t phqv rp# high to output delay 400 400 400 ns r6 t elqx ce# to output in low z 3 0 0 0 ns r7 t glqx oe# to output in low z 3 0 0 0 ns r8 t ehqz ce# high to output in high z 3 55 55 55 ns r9 t ghqz oe# high to output in high z 3 10 10 15 ns r10 t oh output hold from address, ce# or oe# change, whichever occurs first 3000ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. see ordering information for device speeds (valid operational combinations). 5. see transient input/output reference waveform and transient equivalent testing load circuit (high speed configuration) for testing characteristics. 6. see transient input/output reference waveform and transient equivalent testing load circuit (standard configuration) for testing characteristics.
e byte-wide smart 5 flashfile? memory family 31 product preview v cc address stable device address selection ih v il v addresses (a) ih v il v ih v il v ce# (e) oe# (g) data valid standby ih v il v we# (w) data (d/q) (dq0-dq7) ol v oh v high z valid output high z ih v il v rp# (p) r1 r3 r4 r7 r6 r2 r5 r8 r9 r10 figure 15. ac waveform for read operations 6.2.5 commercial temperature reset operations ih v il v rp# (p) ih v il v ry/by# (r) p1 p2 figure 16. ac waveform for reset operation # sym parameter notes min max unit p1 t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) 100 ns p2 t plrh rp# low to reset during block erase, program, or lock-bit configuration 2,3 12 s notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted when the wsm is not busy (ry/by# = 1), the reset will complete within 100 ns. 3. a reset time, t phqv , is required from the latter of ry/by# or rp# going high until outputs are valid.
byte-wide smart 5 flashfile? memory family e 32 product preview 6.2.6 commercial temperature ac characteristics - write operations (1,2) commercial temperature write operations for 4-, 8-, and 16-mbit smart 5 flashfile? memories at t a = 0c to +70c versions (4) 5v 5%, 5v 10% v cc valid for all speeds unit # sym parameter notes min max w1 t phwl (t phel ) rp# high recovery to we# (ce#) going low 3 1 s w2 t elwl (t wlel ) ce# (we#) setup to we# (ce#) going low 7 0 ns w3 t wp write pulse width 7 50 ns w4 t dvwh (t dveh ) data setup to we# (ce#) going high 4 40 ns w5 t avwh (t aveh ) address setup to we# (ce#) going high 4 40 ns w6 t wheh (t ehwh ) ce# (we#) hold from we# (ce#) high 0 ns w7 t whdx (t ehdx ) data hold from we# (ce#) high 5 ns w8 t whax (t ehax ) address hold from we# (ce#) high 5 ns w9 t wph write pulse width high 8 25 ns w10 t phhwh (t phheh ) rp# v hh setup to we# (ce#) going high 3 100 ns w11 t vpwh (t vpeh )v pp setup to we# (ce#) going high 3 100 ns w12 t whgl (t ehgl ) write recovery before read 0 ns w13 t whrl (t ehrl ) we# (ce#) high to ry/by# going low 90 ns w14 t qvph rp# v hh hold from valid srd, ry/by# high 3,5 0 ns w15 t qvvl v pp hold from valid srd, ry/by# high 3,5 0 ns notes: 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. a write operation can be initiated and terminated with either ce# or we#. 3. sampled, not 100% tested. 4. refer to table 3 for valid a in and d in for block erase, program, or lock-bit configuration. 5. v pp should be held at v pph1/2 (and if necessary rp# should be held at v hh ) until determination of block erase, program, or lock-bit configuration success (sr.1/3/4/5 = 0). 6. see ordering information for device speeds (valid operational combinations). 7. write pulse width (t wp ) is defined from ce# or we# going low (whichever goes low last) to ce# or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . if ce# is driven low 10 ns before we# going low, we# pulse width requirement decreases to t wp - 20 ns. 8. write pulse width high (t wph ) is defined from ce# or we# going high (whichever goes high first) to ce# or we# going low (whichever goes low last). hence, t wph = t whwl = t ehel = t whel = t ehwl .
e byte-wide smart 5 flashfile? memory family 33 product preview w3 addresses [a] data [d/q] ih v il v ih v il v ih v il v ih v il v il v in d in a in a valid srd in d high z ih v il v v [v] pp ab c d f e pph2,1 v pplk v in d rp# [p] hh v il v ih v ry/by# [r] ih v il v ce# (we#) [e(w)] we# (ce#) [w(e)] oe# [g] w1 w2 w4 w5 w6 w9 w7 w16 w12 w8 w13 w10 w15 w14 w11 notes: a. v cc power-up and standby. b. write block erase or program setup. c. write block erase confirm or valid address and data. d. automated erase or program delay. e. read status register data. f. write read array command. figure 17. ac waveform for write operations
byte-wide smart 5 flashfile? memory family e 34 product preview 6.2.7 commercial temperature block erase, program, and lock-bit configuration performance (3,4,5) v cc = 5v 0.5v, 5v 0.25v, t a = 0c to +70c 5v v pp 12v v pp # sym parameter notes min typ (1) max min typ (1) max unit w16 t whrh1 t ehrh1 program time 2 6.5 8 tbd 4.8 6 tbd s block program time 2 0.4 0.5 tbd 0.3 0.4 tbd sec w16 t whrh2 t ehrh2 block erase time 2 0.9 1.1 tbd 0.3 1.0 tbd sec w16 t whrh3 t ehrh3 set lock-bit time 2 9.5 12 tbd 7.8 10 tbd s w16 t whrh4 t ehrh4 clear block lock-bits time 2 0.9 1.1 tbd 0.3 1.0 tbd sec w16 t whrh5 t ehrh5 program suspend latency time 56 45s w16 t whrh5 t ehrh5 erase suspend latency time 9.6 12 9.6 12 s notes: 1. typical values measured at t a = +25c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled, but not 100% tested. 5. reference the ac waveform for write operations figure 17.
e byte-wide smart 5 flashfile? memory family 35 product preview 6.3 extended temperature operating conditions except for the specifications given in this section, all dc and ac characteristics are identical to those give in commercial temperature specifications. see the section 6.2 for commercial temperature specifications. extended temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature -40 +85 c ambient temperature 6.3.1 extended temperature dc characteristics extended temperature dc characteristics for 4-, 8-, and 16-mbit smart 5 flashfile? memories 5.0v v cc test sym parameter notes typ max unit conditions i ccd v cc deep power-down current 1 20 m a rp# = gnd 0.2v i out (ry/by#) = 0 ma note: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). contact intels application support hotline or your local sales office for information about typical specifications. 6.3.2 extended temperature ac characteristics - read-only operations (1) extended temperature read-only operations for 4-, 8-, and 16-mbit smart 5 flashfile? memories at t a = -40c to +85c versions (3) 5v 10% v cc C100/C110 # sym parameter notes min max unit r1 t avav read cycle time 4, 8 mbit 100 ns 16 mbit 110 ns r2 t avqv address to output delay 4, 8 mbit 100 ns 16 mbit 110 ns r3 t elqv ce# to output delay 4, 8 mbit 2 100 ns 16 mbit 2 110 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. see ordering information for device speeds (valid operational combinations).
byte-wide smart 5 flashfile? memory family e 36 product preview appendix a ordering information product line designator for all intel flash products operating temperature / package e = com. temp. 40-lead tsop te = ext. temp. 40-lead tsop pa = com. temp. 44-lead psop tb = ext. temp. 44-lead psop e28f0 4 0s5 - access speed (ns) 85 ns (5v, 30 pf), 90 ns (5v) 8 05 voltage options (v cc /v pp ) 5 = smart 5 flash (5v / 5v and 12v) product family s = flashfile? memory device density 004 = 4-mbit 008 = 8-mbit 016 = 16-mbit valid operational combinations order code by density 5v v cc 4 mbit 8 mbit 16 mbit 10% v cc 100 pf load 5% v cc 30 pf load commercial temperature e28f004s5-85 e28f008s5-85 e28F016S5-95 C90/C100 (1) C85/C95 (1) e28f004s5-120 e28f008s5-120 e28F016S5-120 C120 pa28f004s5-85 pa28f008s5-85 pa28F016S5-95 C90/C100 (1) C85/C95 (1) pa28f004s5-120 pa28f008s5-120 pa28F016S5-120 C120 extended temperature te28f004s5-100 te28f008s5-100 te28F016S5-110 C100/C110 (1) tb28f004s5-100 tb28f008s5-100 tb28F016S5-110 C100/C110 (1) note: 1. valid access time for 16-mbit byte-wide flashfile memory.
e byte-wide smart 5 flashfile? memory family 37 product preview appendix b additional information (1,2) order number document/tool 290598 byte-wide smart 3 flashfile? memory family datasheet 290600 byte-wide smartvoltage flashfile? memory family datasheet 292183 ab-64 4-, 8-, 16-mbit byte-wide flashfile? memory family overview 292094 ap-359 28f008sa hardware interfacing 292099 ap-364 28f008sa automation and algorithms 292123 ap-374 flash memory write protection techniques 292180 ap-625 28f008sc compatibility with 28f008sa 292182 ap-627 byte-wide flashfile? memory family software drivers contact intel/distribution sales office 4-, 8-, and 16-mbit schematic symbols contact intel/distribution sales office 4-, 8-, and 16-mbit timingdesigner* files contact intel/distribution sales office 4-, 8-, and 16-mbit vhdl and verilog models contact intel/distribution sales office 4-, 8-, and 16-mbit ibis models note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools.

▲Up To Search▲

Price & Availability of 28F016S5

	To Download 28F016S5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .